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ics for communications content addressable memory element came pxb 4360 f version 1.1 data sheet 07.2000 version 1.1
3;%) 5hylvlrq+lvwru\&xuuhqw9huvlrq previous version: preliminary data sheet 11.97 (ds 2) page (in previous version) page (in current version) subjects (major changes since last revision) the data sheet has been reorganized. i om ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of infineon technologies ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , digitape ? are trademarks of infineon technologies ag. all other brand or product names, hardware or software names are trademarks or registered trademarks of their respective companies or organizations. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com. (glwlrq this edition was realized using the software system framemaker a . 3xeolvkhge\ ,qilqhrq7hfkqrorjlhv$* 6& %dodqvwud?h 0?qfkhq ? infineon technologies ag 2000. all rights reserved. $wwhqwlrqsohdvh as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for ap- plications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the infineon technologies companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. 3dfnlqj please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &rpsrqhqwvxvhglqolihvxssruwghylfhvruv\vwhpvpxvwehh[suhvvo\dxwkrul]hgiruvxfksxusrvh critical components 1 of infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be ex- pected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or main- tain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
3;%) 7deohri&rqwhqwv 3djh data sheet 0-3 07.2000 2yhuylhz 1.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6\vwhp,qwhjudwlrq )xqfwlrqdo2yhuylhz 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( 4.1 programming of the search and search result pattern . . . . . . . . . . . . . . . . . . . . 20 4.2 reading the search pattern for a predefined lci value . . . . . . . . . . . . . . . . . . . 21 4.3 configuration and testing of the came . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 search operation for cell processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.1 data structure of request commands for 16-bit mode . . . . . . . . . . . . . . . . . . . . 23 4.4.2 data structure of the request commands for 32-bit mode . . . . . . . . . . . . . . . . . 25 5hjlvwhuv 5.1 write data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 search address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 address register (dlci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 search result data register (slci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 read data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 description of status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.7 testmode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7.1 data field of testmode register (selection is mode) . . . . . . . . . . . . . . . . . . . . 39 5.7.2 data field of testmode register (selection is tmode) . . . . . . . . . . . . . . . . . . . 41 5.7.3 data field of testmode register (selection is tmux) . . . . . . . . . . . . . . . . . . . . . 42 5.7.4 data field of testmode register (selection is ver0) . . . . . . . . . . . . . . . . . . . . . 42 5.7.5 data field of testmode register (selection is ver1) . . . . . . . . . . . . . . . . . . . . . 43 5.7.6 data field of testmode register (selection is ver2) . . . . . . . . . . . . . . . . . . . . . 43 5.7.7 data field of testmode register (selection is ver3) . . . . . . . . . . . . . . . . . . . . . 44 ,qwhuidfh'hvfulswlrq 6.1 data bus and address bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2 cascade interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.1 cascade logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 clock and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4 boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5 microprocessor and control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6 reference for internal current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3;%) 7deohri&rqwhqwv 3djh data sheet 0-4 07.2000 (ohfwulfdo&kdudfwhulvwlfv 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.3 dc characteristics for all interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.5.1 boundary-scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.5.2 ac characteristics of came data interface to the alp . . . . . . . . . . . . . . . . . . . . 61 7.5.3 ac characteristics of came cascade interface . . . . . . . . . . . . . . . . . . . . . . . . . 63 3dfndjh2xwolqhv 5hihuhqfhv $furq\pv
3;%) /lvwri)ljxuhv 3djh data sheet 0-5 07.2000 figure 1 chipset configuration for main atm layer functionality . . . . . . . . . . . . . . . . . . . 7 figure 2 chipset configuration for main atm layer functionality plus full oam . . . . . . . 8 figure 3 chipset configuration for main atm layer functionality plus full oam and arbitrary header translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 miniswitch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5 line card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6 came logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7 came pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8 alp and came application for 8k connections . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9 alp and came application for 16k connections . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10 block diagram of the came . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 state diagram of status generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12 cascade interface - interconnection of 2 came chips . . . . . . . . . . . . . . . . . . . . 46 figure 13 clock interface of the came . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 14 example for vbias reference voltage circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 15 input/output waveform for ac measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 16 boundary-scan test interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 17 example of execution timing for write command (request #4) . . . . . . . . . . . . 61 figure 18 came read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 19 came write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 20 timing of cascade interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 21 sorts of packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3;%) /lvwri7deohv 3djh data sheet 0-6 07.2000 table 1: data interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 2: cascade interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 3: selection criteria for different instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 4: responding device and overall result after search operation . . . . . . . . . . . . 49 table 5: overall status in case of errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 6: boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 7: came boundary scan table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 9: operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 10: dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 11: capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 12: boundary-scan test interface ac timing characteristics . . . . . . . . . . . . . . . . . 60 table 13: duration of command execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 14: parameters for read/write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 15: cascade interface timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3;%) data sheet 1-7 07.2000 2yhuylhz 2yhuylhz the pxb 4360 f atm content addressable memory element (came) is a member of the infineon atm622 chip set. the entire chip set consists of: ? pxb 4330 e atm buffer manager (abm) ? pxb 4340 e atm oam processor (aop) ? pxb 4350 e atm layer processor (alp) ? pxb 4360 f content addressable memory element (came) main atm layer functionality is achieved with only two chips, alp and abm. the combination of these two devices provides elementary atm functionality such as header translation, policing, oam support, multicast, and traffic management (see iljxuh ). the functionality is upgradeable to full oam support by the aop (see iljxuh ) and to arbitrary header translation by the came (see iljxuh ). )ljxuh &klsvhw&rqiljxudwlrqiru0dlq$70/d\hu)xqfwlrqdolw\ utopia pol. ram pointer ram cell ram phys conn. ram conn. ram cell ram utopia utopia switch (loop) pxb 4350 e alp pxb 4330 e abm
3;%) data sheet 1-8 07.2000 2yhuylhz )ljxuh &klsvhw&rqiljxudwlrqiru0dlq$70/d\hu)xqfwlrqdolw\3oxv)xoo2$0 )ljxuh &klsvhw&rqiljxudwlrqiru0dlq$70/d\hu)xqfwlrqdolw\3oxv)xoo2$0dqg $uelwudu\+hdghu7udqvodwlrq utopia utopia utopia pol. ram pointer ram cell ram phys conn. ram conn. ram conn. ram conn. ram cell ram s wit ch switch (loop) pxb 4330 e abm pxb 4350 e alp pxb 4340 e aop utopia utopia utopia pol. ram pointer ram cell ram phys conn. ram came conn. ram conn. ram conn. ram cell ram s wit ch switch (loop) pxb 4330 e abm pxb 4350 e alp pxb 4340 e aop
3;%) data sheet 1-9 07.2000 2yhuylhz the atm 622 layer devices can be used as .... ...a full switch in: adsl concentrators / multiplexers (dslam) access multiplexers access concentrators multiservice switches ...line card in: workgroup switches edge switches core switches )ljxuh 0lqlvzlwfk&rqiljxudwlrq $/3 $23 utopia utopia $%0 utopia
3;%) data sheet 1-10 07.2000 2yhuylhz )ljxuh /lqh&dug&rqiljxudwlrq due to their immensely flexible scaling facilities, feature set, and throughput, the infineon atm622 layer chips are ideal devices for almost any atm system solution. $/3 $23 utopia utopia $%0 utopia 6zlwfk
data sheet 1-11 07.2000 &rqwhqw$gguhvvdeoh0hpru\(ohphqw &$0( 3;%) 9huvlrq &026 7\sh 3dfndjh pxb 4360 f p-tqfp-144-2/-3 p-tqfp-144-2 / -3 )hdwxuhv ? alp co-processor for address reduction to search for a port number pn, vpi and vci the corresponding local connection identifier lci ? delivers search result during one cell cycle for bit rates up to 686 mbit/s ? came supports up to 8192 search entries ? master or slave mode is selectable to cascade 2 came chips to support up to 16384 search entries ? 16-bit or 32-bit data interface is selectable; alp uses the 16-bit interface ? microprocessor interface is not necessary as came is configurated via address and data bus ? three search modes are supported: - search for lci and the corresponding pn, vpi and vci - search for pn, vpi and vci the corresponding lci - search for pn and vpi the corresponding first valid lci for f4 oam cells ? status report provides: - information on search result: single match, mismatch or multimatch - information on whether the connection is valid or invalid for a given lci, pn, vpi and vci - information on whether the vp is terminated or not for a given lci, pn, vpi and vci ? parity error indication for data bus and came cascade error indication ? boundary scan support according to jtag ? technology: - tqfp-144 package - 3.3 v power supply - typical power dissipation 0.3 w - temperature range from 0c to +70c
3;%) data sheet 1-12 07.2000 /rjlf6\pero )ljxuh &$0(/rjlf6\pero pxb 4360 came alp - data interface test/jtag interface came cascade interface alp - address interface f
3;%) data sheet 1-13 07.2000 3lq&rqiljxudwlrq (top view) )ljxuh &$0(3lq&rqiljxudwlrq came pxb 4360 f cc v cc v cc v v cc dat19 37 144 itp09962 tmd0 gnd dat18 gnd gnd tmd1 dat17 tmd2 dat16 gnd gnd tmd3 dat15 tmd4 dat14 gnd gnd tmd5 dat13 tmd6 dat12 gnd gnd tmd7 dat11 co0 clk gnd gnd co1 dat10 co2 dat9 gnd gnd ci0 dat8 ci1 dat7 gnd gnd ci2 dat6 vbias dat5 rbias gnd gnd dat4 gnd dat3 tdo gnd gnd gnd tdi en16 tms ca gnd gnd tck gnd trst gnd dat32 gnd adr0 dat31 gnd adr1 dat30 gnd adr2 dat29 gnd adr3 dat28 gnd res dat27 gnd we dat26 gnd oe dat25 gnd cs dat24 gnd gnd dat23 gnd gnd dat0 dat22 gnd dat21 dat1 gnd dat20 dat2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 38 142 39 141 40 140 139 42 138 43 137 44 136 45 135 46 134 47 133 48 132 49 131 50 130 129 52 128 53 127 54 126 55 125 56 124 57 123 58 122 59 121 60 120 119 62 118 63 117 64 116 65 115 66 114 67 113 68 112 69 111 70 110 109 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 41 71 61 51 cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc
3;%) data sheet 1-14 07.2000 3lq'hilqlwlrqvdqg)xqfwlrqv the following explanations apply to all pins within a field in the following table: pins with a 1) attached are connected with an internal pull up resistor. 3lq'hilqlwlrqvdqg)xqfwlrqv 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq *hqhudoslqv 20 res i hardware reset signal active low 54 clk i clock input of bus interface 'dwddqg$gguhvv%xv,qwhuidfhehwzhhq&$0(dqg$/3slqv 99, 97, 95, 93, 91, 89, 87, 85, 83, 81, 77, 76, 74, 72, 70, 68, 66, 64, 62, 60, 58, 56, 52, 50, 48, 46, 44, 42, 40, 38, 36, 34, 32 dat (32:0) i/o data bus of bus interface including parity bit (dat(0)). 18, 16, 14, 12 adr (3:0) i address bus of the bus interface 26 cs i chip enable signal of the bus interface. active low 24 oe i output enable signal of the bus interface. active low 22 we i write enable signal of the bus interface. active low 106 en16 i 16-bit mode enable signal of the bus interface. if 0, then dat(16:0) are used. if 1, then dat(32:0) are used. with alp, this pin should be 0 for use with the 16-bit data bus. &$0(&dvfdgh,qwhuidfhslqv
3;%) data sheet 1-15 07.2000 104 ca i cascade interface address input 137, 135, 133 ci (2:0) i cascade interface communication channel 131, 129, 127 co (2:0) o cascade interface communication channel. do not connect in single came application. -7$*,qwhuidfhslqv 9 1) trst i boundary scan test reset active low 3 1) tdi i boundary scan test data input 7 1) tck i boundary scan test clock input 5 1) tms i boundary scan test mode select 144 tdo o boundary scan test data output $gglwlrqdo7hvwslqvslqv 125, 123, 121, 119, 117, 115, 113, 109 tmd (7:0) o test interface. only for test purpose. do not connect. 0lvfhoodqhrxvslqv 139 vbias i analog reference voltage input, used for a precise adjustment of the internal current sources. vbias value: 1.2 v 10%. vbias = 1 switches into powerdown and disables came functionality. 140 rbias o calibration output, used to define the bias current of the internal current sources. a resistor (12.1 k w 1%) must be connected between the rbias pin and ground. 3lq'hilqlwlrqvdqg)xqfwlrqv (contd) 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%) data sheet 1-16 07.2000 6xsso\dqg*1'slqv 1, 4, 8, 11, 15, 19, 23, 27, 29, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 73, 78, 80, 84, 88, 92, 96, 100, 102, 105, 108, 111, 114, 118, 122, 126, 130, 134, 138, 142 vcc (p3v3) supply voltage (nominal 3.3 v) 2, 6, 10, 13, 17, 21, 25, 28, 30, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 75, 79, 82, 86, 90, 94, 98, 101, 103, 107, 110, 112, 116, 120, 124, 128, 132, 136, 141, 143 gnd digital ground (0 v) 8qfrqqhfwhg3lqvslqv unconnected pins 3lq'hilqlwlrqvdqg)xqfwlrqv (contd) 3lq1r 6\pero ,qsxw, 2xwsxw2 )xqfwlrq
3;%) data sheet 2-17 07.2000 6\vwhp,qwhjudwlrq 6\vwhp,qwhjudwlrq one came chip is connected to the alp if only 8k connections are supported. for 16k connections, a second came is cascaded to the first came. the alp is the master device that controls the came. if two came chips are cascaded, the second came must be configured as a slave device to be controlled by the first came, which is operated in master mode. the two configurations are illustrated in iljxuh and iljxuh . . )ljxuh $/3dqg&$0($ssolfdwlrqirun&rqqhfwlrqv arcclk arccs arcwe arcoe arcres arcadr(3:0) ar cdat(16:0) clk cs we oe res adr(3:0) dat(16:0) en16 dat(32:17) 1k w came ca + 3.3 v ci(2:0) co(2:0) (master) gnd 10 k w 1k w gnd alp
3;%) data sheet 2-18 07.2000 6\vwhp,qwhjudwlrq )ljxuh $/3dqg&$0($ssolfdwlrqirun&rqqhfwlrqv arcclk arccs arcwe arcoe arcres arcadr(3:0) ar cda t(16:0) clk cs we oe res adr(3:0) dat(16:0) en16 d at(32:17) gnd came alp clk cs we oe res adr(3:0) dat(16:0) en16 d at(32:17) gnd came ca ca gnd + 3.3 v + 3.3 v ci(2:0) co(2:0) (master) (slave) co(2:0) ci(2:0) + 3.3 v 1k w 1k w 10 k w 10 k w 10 k w 1k w
3;%) data sheet 3-19 07.2000 )xqfwlrqdo2yhuylhz )xqfwlrqdo2yhuylhz the pxb 4360 f is a content addressable memory element (came) that searches for a programmable 32-bit pattern the corresponding programmable 14-bit pattern; or vice versa. additionally, two search bits are provided to support the search for unused entries and to support the search for f4-oam connections in atm. one came supports up to 8192 entries. this can be extended up to 16384 entries by adding a second, cascaded came, without the need for additional glue logic. the target application of the came is the address reduction mechanism for atm cells performed by the infineon atm layer chip alp pxb 4350. the alp extracts the virtual path identifier of a standardized atm cell (vpi) and the virtual channel identifier of a standardized atm cell (vci) from the atm cell header and sends them together with the port number as a 32-bit pattern to the came. after the search procedure of the came, the corresponding 14-bit pattern is sent back to the alp. the 14-bit pattern is used as a local connection identifier (lci) inserted into the atm cell header. herewith, the came translates any arbitrary address, within the address range of 2 32 , into another arbitrary address within the address range of 2 13 (or 2 14 if two came chips are cascaded). the entire search process is completed during one atm cell cycle with a bit rate of 686 mbit/s.
3;%) data sheet 4-20 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( the came can be configured, operated, and tested using six request commands. each request command is a combination of various write and read commands transmitted via the data bus of the came. the address bus selects the request commands. the data flow for writing the search pattern into the came is such that the local connection identifier (lci) defines the address of the memory where the port number (pn), vpi, vci, and the two auxiliary bits p_ip and vcon are stored. the came is operated inversely for cell processing. in the case of cell processing, the pn, vpi, and vci address the memory in which the lci is stored. as well as the lci being transmitted to the alp, a search report is also transmitted. request commands 1 and 2 are activated by the alp during cell processing. request commands 3 through 6 are activated by the microprocessor via the alp because the came has no microprocessor interface. all six request commands are described in the following sections. )ljxuh %orfn'ldjudpriwkh&$0( 3urjudpplqjriwkh6hdufkdqg6hdufk5hvxow3dwwhuq request command number 4 should be used for the set up and release of a connection. first, the lci (14 bits) and the two auxiliary bits vcon and p_ip are written into the write data register and address register via the data bus. subsequently, the pn, vpi, and the vci are written into the write data register. within the 16-bit word, any subdivision by the pn and vpi is allowed. the lci of the address register defines the address of the memory in which the contents of the write data register are written. after writing the entry into memory, status information on the current request is stored in the status register. the status register is read out at the end of each request. write data register (0:33) read data register (0:33) address register (0:13) search address register (0:31) search data register (0:13) pn(3:0), vpi(11:0), vci(15:0), vcon, p_ip lci(13:0) search control logic status register (3:0) data address & wen configuration control logic conf. register (13:0) &$0( memory
3;%) data sheet 4-21 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( the auxiliary bit vcon defines whether an entry is valid or invalid. this mechanism is used to prevent overwriting a valid connection, if the corresponding configuration bit cee 1) in the testmode register is set. a second configuration bit, cle 1) of the testmode register, is available to prevent a multimatch entry. if cle and cee are set, the came checks whether the pn, vpi, and vci already exist. for the case that an entry exists (single or multimatch), the came prevents the writing and outputs a failure report to the status register. for the case that no entry exists (mismatch), the came writes the entry into memory if the lci entry is invalid; otherwise, the writing is also prevented. if cee and cle are not set, there is no checking whether both a valid connection is changed and a multimatch condition is generated. the cee and cle have an influence on the execution time of request command number 4. the auxiliary bit p_ip defines whether the connection point is a path intermediate point. if the p_ip is set, the vci values are ignored during the search process. in the testmode register, the twe bit is provided for testing the memory. if it is set, the write request is converted into a test write request and all memory banks are written simultaneously. 5hdglqjwkh6hdufk3dwwhuqirud3uhghilqhg/&,9doxh request command number 5 should be used to check the search pattern pn, vpi, and vci and the search result pattern vcon and p_ip for a given lci. first, the lci (14 bits) is written into the address register, via the data bus. then the pn, vpi, vci, vcon, and p_ip are written from memory to the read data register. the read data register and the status register are read out via the data bus of the came. in the testmode register, the tre bit is provided for testing the memory. if it is set, the read request is converted into a test read request and all memory banks are read simultaneously. &rqiljxudwlrqdqg7hvwlqjriwkh&$0( request command number 3 should be used to search for a search pattern with deactivated search fields, as defined in the testmode register. this request command should be activated by the microprocessor via the alp and the came interface. it is not used during normal cell processing. first, the pn, vpi, and vci are written into the search address register, via the data bus. after a predefined search period, the search results (lci and the two auxiliary bits vcon and p_ip) are written into the search data register. the status information in the status register and the contents of the search data register are read out via the data bus of the came. in the testmode register, the bits vcen, vpen, and vset are provided to define whether the vci or the pn and vpi are ignored. furthermore, it is possible to search for invalid and free entries, identified by vcon as equal to zero. additionally, a tse bit is implemented to convert the search request into a test search request which compares all memory banks in parallel. request command number 6 is implemented to configure the came for operation and test. this request is a substitute for the microprocessor interface. the configuration and test mode commands are written into the testmode register via the data bus of the came. herewith it is possible to: ? check the cascade interface between the master and slave came devices ? check the parity of the data bus and address bus of the came ? read the version number of the came 1) note that cee and cle are not supported by the alp
3;%) data sheet 4-22 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( ? configure the response on write request command number 4 ? configure the response on search request command number 3 ? configure the test functions of the came. 6hdufk2shudwlrqiru&hoo3urfhvvlqj two search request commands are supported by the came. search request command number 1 is used for search processing of f4-oam cells at the vp termination point. normally, the f4-oam cells are identified by vci value 3 or 4 for segment or end-to-end flow. the alp identifies the f4-oam cells and uses search request command number 1. herewith, the pn and vpi are written into the search address register via the data bus of the came. after a predefined search period, the search results (lci and the two auxiliary bits vcon and p_ip) are written into the search data register. subsequently, the search data and status information are read from the alp. in the case of a valid search result, the lci value is written into the gfc, vpi and udf1 fields of the atm cell. herewith, the came and alp borrow a vci from the user cell which identifies the f4-oam cells as vci value 3 or 4 in order to transmit the f4-oam cell to the aop. this mechanism reduces the number of lci needed for to transport f4-oam cells between the alp and the aop. the alp ignores the multimatch alarm from the came for the f4-oam cells as it is obvious that a terminated vp delivers a match for all vcis if only the pn and vpi value are used as a search pattern. the lci value used is the lowest lci. search request number 2 is used for search processing of cells belonging to a vc or vp connection. this search request is identical to search request command 1 except that the vci value is also written into the search address register. for vp connections, the auxiliary bit p_ip must be set which suppresses the vci search pattern. herewith, only the pn and vpi values are considered. the data structures of the six request commands and the corresponding write and read commands for the 16-bit and 32 bit modes are described in the following sections.
3;%) data sheet 4-23 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( 'dwd6wuxfwxuhri5htxhvw&rppdqgviru%lw0rgh came data bit (16) is used as parity line and completes the arcdat(1:15) and acradr(0:3) to odd parity. note: shaded fields represent unused bits. 5htxhvw1xpehu 6hdufk3urfhvvlqjiru2$0))orz 5htxhvw1xpehu 6hdufksurfhvvlqjiru$70&hoovehorqjlqjwr93&dqg9&& 5htxhvw1xpehu 6hdufk3urfhvvlqjdfwlydwhge\wkh0lfursurfhvvru 1) structure applies to 4-bit pn and 12-bit vpi. if 6-bit pn and 10-bit vpi are selected, the structure of the first dword is bit 15..10 = pn(5:0), bit 9..0 = vpi(9:0) for all requests. bit:1514131211109876543210 write to address c h pn(3:0) vpi(11:0) wait for command execution read from address 6 h v i lci(13:0) read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address d h pn(3:0) vpi(11:0) write to address 5 h vci(15:0) wait for command execution read from address 6 h v i lci(13:0) read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address e h pn(3:0) vpi(11:0) write to address 6 h vci(15:0) wait for command execution read from address 6 h v i lci(13:0) read from address e h s3 s2 s1 s0
3;%) data sheet 4-24 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( 5htxhvw1xpehu :ulwh&rppdqgiru6hwxsdqg5hohdvhri&rqqhfwlrqve\wkh0lfursurfhvvru 5htxhvw1xpehu 5hdg&rppdqgiru9hulilfdwlrqriwkh&rqqhfwlrq(qwu\e\wkh0lfursurfhvvru 5htxhvw1xpehu &$0(7hvwdqg&rqiljxudwlrq&rppdqge\wkh0lfursurfhvvru bit:1514131211109876543210 write to address 2 h v i lci(13:0) write to address b h pn(3:0) vpi(11:0) write to address 3 h vci(15:0) wait for command execution read from address 6 h read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address 0 h lci(13:0) wait for command execution read from address 1 h pn(3:0) vpi(11:0) read from address 9 h vci(15:0) read from address 6 h vi read from address e h s3 s2 s1 s0 bit:1514131211109876543210 write to address 7 h testmode(13:0) wait for command execution read from address 7 h testmode(13:0) read from address f h s3 s2 s1 s0
3;%) data sheet 4-25 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( 'dwd6wuxfwxuhriwkh5htxhvw&rppdqgviru%lw0rgh note: shaded fields represent unused bits. 5htxhvw1xpehu 1) 6hdufk3urfhvvlqjiru2$0))orz 5htxhvw1xpehu 6hdufksurfhvvlqjiru$70&hoovehorqjlqjwr93&dqg9&& 5htxhvw1xpehu 6hdufk3urfhvvlqjdfwlydwhge\wkh0lfursurfhvvru 1) structure applies to 4-bit pn and 12-bit vpi. if 6-bit pn and 10-bit vpi are selected, the structure of the first dword is bit 31..26 = pn(5:0), bit 25..16 = vpi(9:0) for all requests. bit: write to address 4 h of came pn(3:0) vpi(11:0) wait for command execution read from address 6 h of came s3s2s1s0 v i lci(13:0) bit: write to address 5 h of came pn(3:0) vpi(11:0) vci(15:0) wait for command execution read from address 6 h of came s3s2s1s0 v i lci(13:0) bit: write to address 6 h of came pn(3:0) vpi(11:0) vci(15:0) wait for command execution read from address 6 h of came s3s2s1s0 v i lci(13:0)
3;%) data sheet 4-26 07.2000 'dwd)orzdqg)xqfwlrqdo'hvfulswlrqriwkh&$0( 5htxhvw1xpehu :ulwh&rppdqgiru6hwxsdqg5hohdvhri&rqqhfwlrqve\wkh0lfursurfhvvru 5htxhvw1xpehu 5hdg&rppdqgiru9hulilfdwlrqriwkh&rqqhfwlrq(qwu\e\wkh0lfursurfhvvru 5htxhvw1xpehu &$0(7hvwdqg&rqiljxudwlrq&rppdqge\wkh0lfursurfhvvru 1rwh 7kh,elwuhsuhvhqwvwkh3b,3iodjwkh9elwuhsuhvhqwvwkh9&21iodj bit: write to address 2 h of came v i lci(13:0) write to address 3 h of came pn(3:0) vpi(11:0) vci(15:0) wait for command execution read from address 6 h of came s3s2s1s0 bit: write to address 0 h of came lci(13:0) wait for command execution read from address 1 h of came pn(3:0) vpi(11:0) vci(15:0) read from address 6 h of came s3s2s1s0 v i bit: write to address 7 h of came testmode(13:0) wait for command execution read from address 7 h of came s3s2s1s0 testmode(13:0)
3;%) data sheet 5-27 07.2000 5hjlvwhuv 5hjlvwhuv a request command is a sequence of write and read commands at different addresses. the address selects the register and the consequent action performed by the came. therefore, different request commands can write to or read from the same register. :ulwh'dwd5hjlvwhuv each of these registers contains a complete entry consisting of pn/vpi/vci, the p_ip flag and the vcon flag. the registers are loaded from the bus interface at the beginning of write request #4. during request #4, their contents are transferred to the line in came memory which is selected with the address register (dlci). write address 2 h , 3 h , b h value after reset undefined 1rwh 6wuxfwxuhdssolhvwrelw31dqgelw93,,ielw31dqgelw93,duhvhohfwhgwkhvwuxfwxuhlvelw 31dqgelw 93,irudoouhjlvwhuvzlwk31dqg93, vcon p_ip pn(3:0) vpi(11:8) vpi(7:0) vci(15:8) vci(7:0) 16-bit mode request 4: 2 h for vcon, p_ip 3 h for vci(15:0) b h for pn(3:0), vpi(11:0) 32-bit mode request 4: 2 h for vcon, p_ip 3 h for pn(3:0), vpi(11:0), vci(15:0)
3;%) data sheet 5-28 07.2000 5hjlvwhuv 9&21 valid connection flag: 0 connection not valid. 1 connection valid. 3b,3 path intermediate point flag: 0 address reduction is performed over pn, vpi and vci. 1 path intermediate point; address reduction is performed only over pn and vpi. 31 port number 93, vpi value of the atm header. pn and vpi are in a 16-bit field. within the 16 bits, any subdivision into the pn and vpi is allowed. 9&, vci value of the atm header.
3;%) data sheet 5-29 07.2000 5hjlvwhuv 6hdufk$gguhvv5hjlvwhu these registers contain the pn, vpi, vci combination which will be compared to all lines in came during search requests #1,#2 and #3. the registers are loaded from the bus interface at the beginning of the respective search request. write address 4 h , 5 h , 6 h , c h , d h , e h value after reset undefined pn(3:0) vpi(11:8) vpi(7:0) vci(15:8) vci(7:0) 16-bit mode request 1: c h for pn (3:0), vpi (11:0) request 2: 5 h for vci (15:0) d h for pn (3:0), vpi (11:0) request 3: 6 h for vci (15:0) e h for pn (3:0), vpi (11:0) 32-bit mode request 1: 4 h for pn (3:0), vpi (11:0) request 2: 5 h for pn (3:0), vpi (11:0), vci (15:0) request 3: 6 h for pn (3:0), vpi (11:0), vci (15:0) 31 port number 93, virtual path identifier value of the atm header. pn and vpi are in a 16-bit field. any subdivision within the 16-bits for the pn and vpi is allowed. 9&, virtual channel identifier value of the atm header.
3;%) data sheet 5-30 07.2000 5hjlvwhuv $gguhvv5hjlvwhu'/&, this register contains the address of the line to which data is written in a write request #4, or from which data is read in a read request #5. the dlci register is loaded from the bus interface at the beginning of the respective read or write request. write address 0 h , 2 h value after reset undefined lci(13:8) lci(7:0) 16-bit mode request 4: 2 h for lci (13:0) request 5: 0 h for lci (13:0) 32-bit mode request 4 2 h for lci (13:0) request 5: 0 h for lci (13:0) /&, local connection identifier
3;%) data sheet 5-31 07.2000 5hjlvwhuv 6hdufk5hvxow'dwd5hjlvwhu6/&, the result of searching in the memory array is the lci value of the first line that matches the data in the spn/svpi/svci registers. this result is stored in the slci register. at the end of all search requests (#1..3), the alp can read the resulting lci from the slci register. for the other requests (# 4 & #5), the lci value is set to zero. read address 6 h value after reset undefined lci(13:8) lci(7:0) 16-bit mode request 1, 2, 3: 6 h for lci (13:0) 32-bit mode request 1, 2, 3: 6 h for lci 13:0) /&, local connection identifier
3;%) data sheet 5-32 07.2000 5hjlvwhuv 5hdg'dwd5hjlvwhu these registers contain a complete entry consisting of pn/vpi/vci, the p_ip flag and the vcon flag. the read data contained in the came memory line, selected with the dlci register contents, is transferred to these registers. at the end of a read request #5, the alp can read the resulting data from the rpn,rvpi,rvci,ri,rv registers. read address 1 h , 6 h , 9 h value after reset undefined vcon p_ip pn(3:0) vpi(11:8) vpi(7:0) vci(15:8) vci(7:0) 16-bit mode request 5: 1 h for pn(3:0), vpi(11:0) 6 h for vcon, p_ip 9 h for vci(15:0) 32-bit mode request 5: 1 h for pn(3:0), vpi(11:0), vci(15:0) 6 h for vcon, p_ip 9&21 valid connection flag: 0 connection not valid. 1 connection valid. 3b,3 path intermediate point flag: 0 address reduction is performed over pn / vpi / vci. 1 path intermediate point; address reduction is performed only over pn / vpi.
3;%) data sheet 5-33 07.2000 5hjlvwhuv 31 port number 93, virtual path identifier value of the atm header. pn and vpi are in a 16-bit field. any subdivision within the 16 bits for the pn and vpi is allowed. 9&, virtual channel identifier
3;%) data sheet 5-34 07.2000 5hjlvwhuv 'hvfulswlrqri6wdwxv,qirupdwlrq status information generated by the control logic in the came indicates the success of commands or detected failures. at the end of each command cycle, status information about the current operation is transferred from the came to the alp. the 4-bit status field consists of two bits (s3,s2) with command independent information and two bits (s1,s0) with command related details. the data bus parity error is returned if a parity error at the data bus interface was detected by the came since the last completed request. in all requests, the master came checks whether the slave also accepted a request. this information is transferred at the cascade interface. if the slave signals at co(1..0) that it has recognized no request the cascade error status is generated in the master (note: if lci 2000..3fff h is accessed in a single came configuration, cascade error is also indicated because this case cannot be distinguished from a two-chip configuration with a defect on the second chip). a command cycle error is internally set after reading the status at the end of a request, or if a write access was performed while a command cycle was running. if a parity error is detected in one of the write accesses at the start of a command, the command is discarded, internal status information is set to parity error, and the control logic waits for one of the two possible final bus read accesses (address #6 or #7). after the final bus read access, the came is ready for the next command cycle. after a command cycle is finished, the internal status contains a command cycle error. this status is changed with the start of a new command cycle. if the start of a command cycle is not recognized by the came, the error status above is still present at the next status read access. for s3/s2 = 1/0, coding of s1/s0 depends on the command just finished in the following way: status information can be read any time at address 6 and address 7. iljxuh at page 35 shows the conditions under which the status information changes. the five states, named as ok, busy, alarm, error(cmd), error(parity) and shown in this figure, are coded by the status bits s3..0. the start of a request can take place in the ok, alarm, or error (cascade or command cycle) state. if a parity error is detected, the parity error state is entered. this state is left only on reading of the status information. all write accesses are ignored while the status is in parity error state. if no parity error has occurred, the command is processed. this is indicated by the busy state. in this state, writing generates a command cycle error and no internal register is changed by the write access. reading is allowed in busy state. depending on the result of the request, either the ok, alarm, or error (cascade or command cycle) status is entered. after reading the status once, the error (command cycle) is entered. this supports the recognition of a missing command cycle start.
3;%) data sheet 5-35 07.2000 5hjlvwhuv )ljxuh 6wdwh'ldjudpri6wdwxv*hqhudwlrq 6wdwxv5hjlvwhu read address 6 h , 7 h , e h , f h value after reset 0000 h s3 s2 s1 s0 16-bit mode request 1, 2, 3, 4, 5: e h for s3, s2, s1, s0 request 6: f h for s3, s2, s1, s0 32-bit mode request 1, 2, 3, 4, 5: 6 h for s3, s2, s1, s0 request 6: 7 h for s3, s2, s1, s0 ok busy error (cmd cyc. or casc.) alarm 1) start of a request (write access) 3) internal processing of request finished 6) status read access 4) error occurred during internal processing 2) parity error occurred at start of a request 5) alarm occurred during internal processing transition conditions: error (parity) 1) 2) 3) 4) or any write 5) 6) 6) 6)
3;%) data sheet 5-36 07.2000 5hjlvwhuv 6 s3 / s2 :s1/s0 00 ok command was executed without problems. indication in s1/s0: s1/s0 = 0/0. 01 busy command execution is still in progress. indication in s1/s0: s1/s0 = 0/0. 10 alarm operation was not successful for came memory content dependent reasons. indication in s1 / s0: 00 mismatch (at search requests #1..3). the search pattern was not found in any line. the lci returned is invalid (01ff h ). 01 multimatch (at search requests #1..3). the search pattern was found in more than one line. the lci of the lowest matching line is returned. 10 test search fault (at search requests #1..3). after test search, the search pattern was not found in all 16 blocks at the same line offset and nowhere else. the lci returned is invalid. 00 refused entry (at write request #4). attempt to write an entry to came which is already stored in a line of this chip (or the second came). this mode can be activated with mode register bit cee. 01 refused line (at write request #4). attempt to write a valid entry in a line already containing valid information. this mode can be activated with mode register bit cle. 00 test read fault (at read request #5). the contents read from all 16 blocks at the same line offset were not equal. the read result returned is invalid. 11 error a hardware error was detected. indication in s1 / s0: 00 data bus parity error. 01 cascade error. 10 command cycle error.
3;%) data sheet 5-37 07.2000 5hjlvwhuv 7hvwprgh5hjlvwhu the testmode register is used in the test request #6. the testmode register acts as an intermediate stage for access to the configuration (mode, tmode), test (tmux) and version (ver0..3) registers which are selected by the selection field. the control field defines the read and modify-and-read operation as well as access to the master or slave device. the data field is used as mode, tmode, and tmux registers as well as version register (ver0..3) selected by the selection register. read/write address 7 h value after reset undefined selection(2:0) control(1:0) data(8) data(7:0) 16-bit mode request 6: 7 h for testmode(13:0) 3-bit mode request 6: 7 h for testmode(13:0) 6hohfwlrq selection field defines which one of the eight registers is selected 000 mode register used for cascade interface test, configuration of the request #3 and #4 001 tmode register used for checking of the internal memory 010 tmux register for test purposes only. 011 reserved 100 read version number octet 0; ver0 register used for reading 101 read version number octet 1; ver1 register used for reading 110 read version number octet 2; ver2 register used for reading 111 read version number octet 3; ver3 register used for reading
3;%) data sheet 5-38 07.2000 5hjlvwhuv &rqwuro control field 0 modify and read; not usable for selection (100:111) 1read &rqwuro control field 0 master is accessed 1 slave is accessed 'dwd data field
3;%) data sheet 5-39 07.2000 5hjlvwhuv 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv02'( for request #1, the vset portion for comparison is lqwhuqdoo\ set to 1, vped is set to 0 and vced set to 1. in request #2, the settings vset = 1, vced = 0 and vped = 0 are used. for request #3, all three vset, vced and vped duhsurjudppdeoh in the mode register. both modes of searching as well as searching for invalid lines are possible under microprocessor control during cell processing. for sw convenience and acceleration of the connection data update, write request #4 may be extended by using the cee and cle bits in the mode register. if cee is set to 1 before writing a pattern to a line, searching for this pattern in the came (and the optional second came) is performed. if this pattern is already present, the command cycle is finished without writing to the line. this failure is reported in the status register. next, if enabled, prior to writing with cle set to 1, the destination line is checked to determine if it already contains a valid entry (with vcon = 1). writing is prevented only if a valid pattern (vcon =1) is intended to be written over a valid entry and the failure is reported in the status field. 1rwh &rppdqg h[hfxwlrq wlph ydulhv zlwk &(( dqg &/( xvdjh 7kh qxpehu ri forfn f\fohv uhtxluhg iru uhtxhvwsurfhvvlqjsurklelwvwkhluxvdjhlq 0elwvv\vwhpv7khfrppdqgh[hfxwlrqwlphvduholvwhg lq wdeoh rq sdjh vced vped vset dpg cio2 cio1 cio0 cle cee 9&(' vci evaluation disable. this bit has no influence on any requests except request #3: 0default 1 vci is ignored in search requests of type #3. 93(' vpi evaluation disable. this bit has no influence on any requests except request #3: 0default 1 pn / vpi is ignored in search requests of type #3. 96(7 for vcon comparison internally set value for search request #3: 0 free empty lines are localized. 1default
3;%) data sheet 5-40 07.2000 5hjlvwhuv '3* disturbed parity generation. generate a bus parity error in the read access at the end of this command cycle. this bit is automatically reset. dpg is not supported by the alp! 0default &,2 ci(2) / co(2) data if this bit is written, it determines the setting of the co(2) output while it is used for cascade interface check. if it is read, it reflects the level at the ci(2) input. ydefault y depends on the ci input with the same index &,2 ci(1) / co(1) data if this bit is written, it determines the setting of the co(1) output while it is used for cascade interface check. if it is read, it reflects the level at the ci(1) input. ydefault y depends on the ci input with the same index &,2 ci(0) / co(0) data if this bit is written, it determines the setting of the co(0) output while it is used for cascade interface check. if it is read, it reflects the level at the ci(0) input. ydefault y depends on the ci input with the same index &/( check of a line before write enable. this means writing of a valid entry (with its vcon bit set to 1) over a valid entry in memory (also with vcon bit contained in this line set to 1) is not performed; instead, in the status field, an alarm is returned. activation of this bit prolongs the write request (restricted usage in 622 mbit/s systems). cle is not supported by the alp! 0default &(( check of an entry before write enable. search is performed for occurrence of write pattern in the came (and a cascaded came, if connected). if the pattern is already present, the related line will not be updated and an alarm is returned in the status field. activation of this bit prolongs the write request (restricted usage in 622 mbit/s systems). cee is not supported by the alp! 0default
3;%) data sheet 5-41 07.2000 5hjlvwhuv 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv702'( tmode register use is allowed only if the mode register is set to the default values mentioned in vhfwlrq on page 39. the tmode register bits cause the following functional changes: reserved(5) reserved(4:0) twe tre tse uhvhuyhg reserved, do not activate. 000000 default 7:( test write enable. enables writing to all memory banks in parallel. this bit changes a write request #4 to a test write request. 0default 75( test read enable. enables parallel reading from all banks at the same offset. this bit changes a read request #5 to a test read request. 0default 76( test search enable. enables parallel comparing in all banks. this bit changes a search request #3 to a test search request. 0default
3;%) data sheet 5-42 07.2000 5hjlvwhuv 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv708; 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv9(5 tmux(8) tmux(7:0) 708; for test only. this register should be set to 0 for normal operation (tmux disabled): 000000000 default ver0(8) ver0(7:0) 9(5 0 value 9(5 version number, octet 0. version number bits 7..0 contain 2f h .
3;%) data sheet 5-43 07.2000 5hjlvwhuv 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv9(5 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv9(5 ver1(8) ver1(7:0) 9(5 0value 9(5 version number, octet 1. version number bits 15..8 contain 70 h . ver2(8) ver2(7:0) 9(5 0value 9(5 version number, octet 2. version number bits 23..16 contain 0b h .
3;%) data sheet 5-44 07.2000 5hjlvwhuv 'dwd)lhogri7hvwprgh5hjlvwhu6hohfwlrqlv9(5 ver3(8) ver3(7:0) 9(5 0 value 9(5 version number, octet 3. version number bits 31..24 contain 0b h .
3;%) data sheet 6-45 07.2000 ,qwhuidfh'hvfulswlrq ,qwhuidfh'hvfulswlrq 'dwd%xvdqg$gguhvv%xv,qwhuidfh all communication with alp is done using the data interface. the data interface consists of the following signals, as shown in wdeoh : 1) dat(15:1) are needed with alp v1.1. dat(32:17) are reserved for future use. came will be accessed only if ce is low at the rising edge of clk. if we is low at the time, a write cycle will be executed; if w e is high, a read cycle will be executed. the oe signal controls the came output buffers for read accesses only. the en16 signal determines data bus width, which is 16-bit for en16 at low level, and 32-bit otherwise. this signal is intended for static adjustment of bus width. parity generation in 16-bit mode extends over dat(16..0) and adr(3..0). in 32-bit mode, it extends over dat(32..0) and adr(3..0). in 32-bit interface mode, adr(3) is not needed and must be connected to ground; thus, parity generated over dat(32..0) and adr(2..0) is accepted correctly. in both cases, dat(0) is used as a parity line and completes the corresponding dat and adr lines to odd parity. in 16-bit mode, only the lower part of the data bus is used. the upper bus half (index 17..32) is ignored during write accesses to came and is 0 during read accesses. 7deoh 'dwd,qwhuidfh6ljqdov 6ljqdo1dph ([sodqdwlrq 7\sh dat(0) odd parity. selected to create parity over adr and dat bidirectional dat(31..1) 1) data bus bidirectional dat(32) data bus bidirectional adr(2..0) address bus input adr(3) address bus input we write enable input oe output enable input ce chip enable input clk clock input en16 selection of bus width input
3;%) data sheet 6-46 07.2000 ,qwhuidfh'hvfulswlrq &dvfdgh,qwhuidfh for more demanding applications, two came chips can be cascaded to build up one virtual device with double capacity and the identical physical bus interface to an external controller. the cascade interface is used for this purpose and consists of the co(2..0) outputs and the ci(2..0) and ca inputs as shown in iljxuh . )ljxuh &dvfdgh,qwhuidfh,qwhufrqqhfwlrqri&$0(&klsv both came chips receive the same requests from alp. depending on the request, the determination of which chip may answer at the end of the request is either known in advance (read, write and test requests #4..6) or results from the operation (search requests #1..3). in the second case, the master must inform the slave of its search result and indicate whether or not it processes the search request. the same report takes place from the slave to the master. this is done with the signals co(1..0). processing the crosswise transferred status information is done according to wdeoh . the timing of this transfer is defined in wdeoh . the interpretation of the co(1..0) signals at this time is done according to wdeoh . in order to avoid bus conflicts on reading of cascaded came chips, the master has the opportunity to disable data output of the slave came using the co(2) signal. this signal is important in case of a parity error, for example. the co(2..0) outputs must be connected to the ci(2..0) inputs of the opposite came. 1k w came ca ci( 0) co(0) ci( 1) ci( 2) co(1) co(2) alp bus interface came (master) ca ci(2:0) co(2:0) 1k w gnd gnd bus interface alp came (slave) ca ci(2:0) co(2:0) 10k w + 3.3 v bus interface a) single came application a) 2 came application
3;%) data sheet 6-47 07.2000 ,qwhuidfh'hvfulswlrq for single chip applications, the came device must be configured as master by ca and the ci(1..0) inputs must be supplied with low level, pretending an always mismatch condition of the non-existent slave. the ci(2) input is not evaluated by a chip configured as master, but it needs connection to ground. &dvfdgh/rjlf if two came chips are cascaded, the selection of which device will react and may respond is made based on the command started. no additional preparation at the bus interface is necessary. in read or write command cycles, the lci - at least part of the command word - 7deoh &dvfdgh,qwhuidfh6ljqdov 6ljqdo 1dph &rgh )xqfwlrq 7\sh ca 0 device is master, its lci range is 0..8191 input 1 device is slave, its lci range is 8192..16383 ci(1..0) 00 a search request (#1..3 or #4 with mode.cee= 1) is running with the result mismatch on the opposite chip input 01 a search request (#1..3 or #4 with mode.cee= 1) is running with the result of single match or multimatch on the opposite chip 10 no request is processed by the opposite chip 11 request #4..6 is processed by the opposite chip ci(2) 0 ci(2) is ignored by a master. a slave interprets ci(2) as follows: data output at dat is prohibited in read cycles input 1 data output at dat is allowed in read cycles co(1..0) 00 a search request (#1..3 or #4 with mode.cee= 1) is running with the result mismatch output 01 a search request (#1..3 or #4 with mode.cee= 1) is running with the result of single match or multimatch 10 no request is processed 11 request #4..6 is processed co(2) 0 co(2) of a slave is undefined.a master outputs co(2) as follows: prohibit data output of a slave in read cycles output 1 allow data output of a slave in read cycles
3;%) data sheet 6-48 07.2000 ,qwhuidfh'hvfulswlrq determines which chip performs the operations and may send back the results to alp. therefore, the chip not selected chip must also wait for the end of the current request before a new request may be started. in search cycles, both came chips start searching in parallel. only one chip will respond to alp, determined by the search result. only for test request #6 must an extra bit, testmode(9), be spent in the instruction word for selection between master and slave. with two cascaded came chips, each came first searches alone. when the match state of master and slave is known, the master reports his local result to the slave. it is only necessary to report mismatch or not mismatch conditions. the same is done by the slave. both chips determine their reaction and the overall status according to wdeoh , which includes all combinations of local master and slave search results. the fields of this table contain the overall status of the result for which device returns the result to alp and which stays inactive. for example, if both chips detect a single match, the slave knows about its own state and the detection of at least an additional match in the master (master.co(2..0) = slave.ci(2..0)) and knows that a global multimatch results. as the slave in this case, it must not respond to alp. the master also detects a global multimatch the same way (slave.co(2..0) = master.ci(2..0)) and responds to alp. 7deoh 6hohfwlrq&ulwhuldiru'liihuhqw,qvwuxfwlrqv &rppdqg7\sh 6hohfwlrqri0dvwhu 6hohfwlrqri6odyh search - requests #1..3 refer to table 4 write - request #4 0 lci 8191 8192 lci 16383 read - request #5 0 lci 8191 8192 lci 16383 test - request #6 testmode(9) = 0 testmode(9) = 1
3;%) data sheet 6-49 07.2000 ,qwhuidfh'hvfulswlrq in summary, the condition for the came to become active at the end of an error-free search cycle is: if the slave receives 00 for mismatch on ci(1..0) and recognizes an internal single match or multimatch condition it may respond to the master; it must not respond in all other cases. a master will not respond at the end of the current command cycle only if it detects an internal mismatch condition and the slave reports at ci(1..0) with 01 no mismatch; in all other cases the master responds. in the case of a communication fault at the beginning of a request, the determination of which chip may respond is not performed. the reason may be a parity error. to avoid bus conflicts, the slave always must be controlled by the master chip for data output in case of reading. this is done by the master with the co(2) signal. if the slave outputs the codes 10 (no request processed) or 11 (request #4..6 processed) at co(1..0) while the master processes a search request, the overall status cascade error is reported by the master. if the master processes one of the requests without searching, then only if the slave outputs the code 10 (no request processed) is the overall status cascade error. in the other cases, no error is recognized. the code 00 from a slave is accepted intentionally, even if it pretends a search operation, because, for non-cascaded applications, the ci(2..0) inputs are connected to ground. finally, if the master holds the internal status data bus parity error or command cycle error, no request is processed by the master. in this case, the slave status is ignored. this behavior is summarized in wdeoh . the master will always report the cascade, parity, and command cycle errors. 7deoh 5hvsrqglqj'hylfhdqg2yhudoo5hvxowdiwhu6hdufk2shudwlrq 0dvwhu'hylfh mismatch master.co(1..0) = 00 single match master.co(1..0) = 01 multimatch master.co(1..0) = 01 6odyh'hylfh mismatch slave.co(1..0) = 00 master: mismatch slave: inactive master: single match slave: inactive master: multimatch slave: inactive single match slave.co(1..0) = 01 master: inactive slave: single match master: multimatch slave: inactive master: multimatch slave: inactive multimatch slave.co(1..0) = 01 master: inactive slave: multimatch master: multimatch slave: inactive master: multimatch slave: inactive
3;%) data sheet 6-50 07.2000 ,qwhuidfh'hvfulswlrq 7deoh 2yhudoo6wdwxvlq&dvhri(uuruv 0dvwhu co(1..0) = 00 or 01 (requests with searching) co(1..0) = 11 (requests without searching) co(1..0) = 10 (no request processed) 6odyh co(1..0) = 00 or 01 see table 4 status of read, write and test requests parity or command cycle error co(1..0) = 11 cascade error reported by the pre- selected device parity or command cycle error co(1..0) = 10 cascade error cascade error parity or command cycle error
3;%) data sheet 6-51 07.2000 ,qwhuidfh'hvfulswlrq &orfndqg5hvhw the system clock is passed to came at the clk input. for typical applications, it will be equal to alp sys_clk/2 = 25.92 mhz. this is the only clock supply for the came (if the bscan interface clock is ignored). it determines operation of the bus interface and the timing of all clocked internal functions. the alp delivers the clk signal for the came without any glue logic, as depicted in iljxuh . )ljxuh &orfn,qwhuidfhriwkh&$0( the reset signal is an active low input. as long as it is connected to a low level, the data bus dat(32..0) will be forced to a high-impedance state, co(2..0) are set to 000. tdo and tmd(7..0) are not influenced. when the transition low ? high is detected at reset , the internal control logic is reset, the internal status is ok and all test function registers are set to their default values as outlined in section 5.7 on page 37. thus, test multiplexer selection and the co(2..0) outputs are influenced. internal registers around the memory array are also cleared. the contents of the memory array are not changed intentionally, but memory protection during reset is not implemented. as long as reset stays at a high level, normal operation will occur. $23 $%0 $/3 3+< &$0( 8wrsld3+< &orfn 6<6&orfn 8wrsld$70 &orfn 6<6&orfn 6<6&orfn 0+] 1:2 &$0(&orfn 6<6&orfn
3;%) data sheet 6-52 07.2000 ,qwhuidfh'hvfulswlrq %rxqgdu\6fdq,qwhuidfh factory test is supported by the boundary scan interface. it consists of four inputs for control of the tap-controller and one output described in table 6. the tap-controller is a part of the bscan logic. according to ieee-standard 1149.1, boundary scan also provides a 32-bit identification register. in came, it contains the boundary scan id number 0b0b702f h . 7deoh %rxqgdu\6fdq,qwhuidfh 6ljqdo ([sodqdwlrq tck clock input tdi serial data input, accepted with rising tck edge tdo serial data output, changes with falling tck edge tms test mode select signal, accepted with rising tck edge, defines tap controller operation mode. trst test interface reset signal, low level initializes the tap-controller asynchronously 7deoh &$0(%rxqgdu\6fdq7deoh %rxqgdu\ 6fdq1xpehu 3,11u 6ljqdo1dph 7\sh 112adr(0) i 214adr(1) i 316adr(2) i 418adr(3) i 520res i 622we i 724oe i 826cs i 932dat(0) o 10 32 dat(0) i 11 34 dat(1) o 12 34 dat(1) i
3;%) data sheet 6-53 07.2000 ,qwhuidfh'hvfulswlrq 13 36 dat(2) o 14 36 dat(2) i 15 38 dat(3) o 16 38 dat(3) i 17 40 dat(4) o 18 40 dat(4) i 19 42 dat(5) o 20 42 dat(5) i 21 44 dat(6) o 22 44 dat(6) i 23 46 dat(7) o 24 46 dat(7) i 25 48 dat(8) o 26 48 dat(8) i 27 50 dat(9) o 28 50 dat(9) i 29 52 dat(10) o 30 52 dat(10) i 31 54 clk i 32 - control pad for dat(32:0) - 33 56 dat(11) o 34 56 dat(11) i 35 58 dat(12) o 36 58 dat(12) i 37 60 dat(13) o 38 60 dat(13) i 7deoh &$0(%rxqgdu\6fdq7deoh (contd) %rxqgdu\ 6fdq1xpehu 3,11u 6ljqdo1dph 7\sh
3;%) data sheet 6-54 07.2000 ,qwhuidfh'hvfulswlrq 39 62 dat(14) o 40 62 dat(14) i 41 64 dat(15) o 42 64 dat(15) i 43 66 dat(16) o 44 66 dat(16) i 45 68 dat(17) o 46 68 dat(17) i 47 70 dat(18) o 48 70 dat(18) i 49 72 dat(19) o 50 72 dat(19) i 51 74 dat(20) o 52 74 dat(20) i 53 76 dat(21) o 54 76 dat(21) i 55 77 dat(22) o 56 77 dat(22) i 57 81 dat(23) o 58 81 dat(23) i 59 83 dat(24) o 60 83 dat(24) i 61 85 dat(25) o 62 85 dat(25) i 63 87 dat(26) o 64 87 dat(26) i 7deoh &$0(%rxqgdu\6fdq7deoh (contd) %rxqgdu\ 6fdq1xpehu 3,11u 6ljqdo1dph 7\sh
3;%) data sheet 6-55 07.2000 ,qwhuidfh'hvfulswlrq 65 89 dat(27) o 66 89 dat(27) i 67 91 dat(28) o 68 91 dat(28) i 69 93 dat(29) o 70 93 dat(29) i 71 95 dat(30) o 72 95 dat(30) i 73 97 dat(31) o 74 97 dat(31) i 75 99 dat(32) o 76 99 dat(32) i 77 104 ca i 78 106 en16 i 79 109 tmd(0) o 80 113 tmd(1) o 81 115 tmd(2) o 82 117 tmd(3) o 83 119 tmd(4) o 84 121 tmd(5) o 85 123 tmd(6) o 86 125 tmd(7) o 87 127 co(0) o 88 129 co(1) o 89 131 co(2) o 90 133 ci(0) i 7deoh &$0(%rxqgdu\6fdq7deoh (contd) %rxqgdu\ 6fdq1xpehu 3,11u 6ljqdo1dph 7\sh
3;%) data sheet 6-56 07.2000 ,qwhuidfh'hvfulswlrq 0lfursurfhvvrudqg&rqwuro,qwhuidfh no microprocessor interface is implemented in the came. in the came, data and control interfaces are identical. for the interface description, refer to "data bus and address bus interface" on page 6-45. the came mode register access takes place with request #6. for details about command transfer, refer to vhfwlrq page 37. 5hihuhqfhiru,qwhuqdo&xuuhqw6rxufhv adjustment of internal current sources is done using the rbias and vbias pins. vbias must be connected to a precision voltage reference with 1.2 v 10%. additionally, between the rbias pin and ground, a resistor with 12.1 k w 1% is necessary. vbias= 1 is interpreted as powerdown and disables the came functionality. . )ljxuh ([dpsohiru9%,$65hihuhqfh9rowdjh&lufxlw 91 135 ci(1) i 92 137 ci(2) i 7deoh &$0(%rxqgdu\6fdq7deoh (contd) %rxqgdu\ 6fdq1xpehu 3,11u 6ljqdo1dph 7\sh gnd gnd v33 vbias c=100nf r=10k lm4041eim3-1.2 ref 1.2v
3;%) data sheet 7-57 07.2000 (ohfwulfdo&kdudfwhulvwlfv (ohfwulfdo&kdudfwhulvwlfv $evroxwh0d[lpxp5dwlqjv 1rwh 6wuhvvhv deryh wkrvh olvwhg khuh pd\ fdxvh shupdqhqw gdpdjh wr wkh ghylfh ([srvxuh wr devroxwh pd[lpxpudwlqjfrqglwlrqviruh[whqghgshulrgvpd\diihfwghylfhuholdelolw\ 2shudwlqj&rqglwlrqv 7deoh $evroxwh0d[lpxp5dwlqjv 3dudphwhu 6\pero /lplw9doxhv 8qlw supply voltage 9 cc -0.5 to 4.6 v input voltage 9 in -0.5 to 9 cc +0.5 v output voltage 9 out v power dissipation 3 v <0.3 w storage temperature 7 s -65 to 150 c 7deoh 2shudwlqj&rqglwlrqv 3dudphwhu 6\pero /lplw9doxhv 8qlw supply voltage 9 cc 3.135 to 3.465 v ground *1' 0v input voltage 9 in 0 to 9 cc v output voltage 9 out 0 to 9 cc v input low voltage 9 in 0 to 0.8 v input high voltage 9 in 2.0 to 9 cc v ambient temperature 7 a 0 to 70 c junction temperature 7 j max. 100 c
3;%) data sheet 7-58 07.2000 (ohfwulfdo&kdudfwhulvwlfv '&&kdudfwhulvwlfvirudoo,qwhuidfhv 7deoh '&&kdudfwhulvwlfv 3dudphwhu 6\pero /lplw9doxhv 8qlw 7hvw&rqglwlrq plq w\s pd[ input low voltage 9 il 00.8v input high voltage 9 ih 2.0 9 cc v output low voltage 9 ol 0.4 v output high voltage 9 oh 2.4 v 9 oh = 9 dd or 9 ss output current at high voltage , oh -8 ma 9 in = 9 cc or 0 v output current at low volt- age , ol 8ma 9 in = 9 cc or 0 v input leakage current at low voltage (all inputs except tck, tms, tdi, trstn) , il -1 1 ma 9 in = 9 cc or 0 v input leakage current at high voltage (all inputs except tck, tms, tdi, trstn) , ih -1 1 ma 9 in = 9 cc or 0 v input leakage current at low voltage (inputs tck, tms, tdi, trstn) , il -1 -14 ma 9 in =0 v input leakage current at high voltage (inputs tck, tms, tdi, trstn) , ih -1 1 ma 9 in = 9 cc
3;%) data sheet 7-59 07.2000 (ohfwulfdo&kdudfwhulvwlfv &dsdflwdqfhv $&&kdudfwhulvwlfv 7 a = 0 to 70 c, 9 cc = 3.3 v 5%, 9 ss = 0 v all inputs are driven to 9 ih = 2.4 v for a logical 1 and to 9 il = 0.4 v for a logical 0 all outputs are measured at 9 h = 2.0 v for a logical 1 and at 9 l = 0.8 v for a logical 0 the ac testing input/output waveforms are shown in iljxuh . )ljxuh ,qsxw2xwsxw:dyhirupiru$&0hdvxuhphqwv 7deoh &dsdflwdqfhv 3dudphwhu 6\pero /lplw9doxhv 8qlw plq pd[ input capacitance & in 5pf input/output capacitance & in/out 7pf
3;%) data sheet 7-60 07.2000 (ohfwulfdo&kdudfwhulvwlfv %rxqgdu\6fdq7hvw,qwhuidfh )ljxuh %rxqgdu\6fdq7hvw,qwhuidfh7lplqj'ldjudp 7deoh %rxqgdu\6fdq7hvw,qwhuidfh$&7lplqj&kdudfwhulvwlfv 1r 3dudphwhu /lplw9doxhv 8qlw 0lq 7\s 0d[ 1 7 tck : period tck 160 ns 1a ) tck : frequency tck 0 6.25 mhz 2 set up time tms, tdi before tck rising 10 ns 3 hold time tms, tdi after tck rising 10 ns 4 delay tck falling to tdo valid 0 30 ns 5 delay tck falling to tdo high impedance 0 30 ns 6 pulse width trst low 100 ns
3;%) data sheet 7-61 07.2000 (ohfwulfdo&kdudfwhulvwlfv $&&kdudfwhulvwlfvri&$0('dwd,qwhuidfhwrwkh$/3 )ljxuh ([dpsohri([hfxwlrq7lplqjiru:ulwh&rppdqg5htxhvw 7deoh 'xudwlrqri&rppdqg([hfxwlrq 3dudphwhu 0d[h[hfxwlrqwlph 8qlw iruelw lqwhuidfh iruelw lqwhuidfh request number 1: cell processing search for pn/vpi reduction 12 13 clock cycles request number 2: cell processing search for, pn/vpi/vci reduction 12 14 clock cycles request number 3: search request by the microprocessor 12 14 clock cycles request number 4: came write command 8 10 1) 1) only this mode is selected by the alp pxb 4350 e. clock cycles extended modes: mode.cee = 0, mode.cle = 1 12 14 clock cycles mode.cee = 1, mode.cle = 0 14 16 clock cycles mode.cee = 1, mode.cle = 1 16 18 clock cycles request number 5: came read command 11 13 clock cycles request number 6: test and configuration of the came 8 9 clock cycles clk cs oe we adr(3:0) dat(16:0) 12 n-1 n start (first write) end (last read)
3;%) data sheet 7-62 07.2000 (ohfwulfdo&kdudfwhulvwlfv )ljxuh &$0(5hdg&\foh )ljxuh &$0(:ulwh&\foh clk cs oe we adr(3:0) dat(16:0) 1 2 3 4 6 5 8 7 clk cs oe adr(3:0) 3 4 dat(16:0) we
3;%) data sheet 7-63 07.2000 (ohfwulfdo&kdudfwhulvwlfv 1) the alp pxb 4350 e uses only the 16-bit access $&&kdudfwhulvwlfvri&$0(&dvfdgh,qwhuidfh )ljxuh 7lplqjri&dvfdgh,qwhuidfh 7deoh 3dudphwhuviru5hdg:ulwh$ffhvv 1r 3dudphwhu /lplw9doxhv 8qlw plq w\s pd[ 1 clk frequency 0.01 25.92 mhz 2 clk duty cycle 40 60 % 3 set up time of cs , we , adr and dat in read and write cycle to clk - 4ns 4 hold time of cs , we , adr and dat in read and write cycle from clk - 4ns 5a 1) data access of dat in read cycle from clk - (32-bit access) 35 ns 5b 1) data access of dat in read cycle from clk - (16-bit access) 19 ns 6 data hold of dat in read cycle from clk - 4ns 7oe low of dat in read cycle to output active 21 ns 8oe high of dat in read cycle to output z 21 ns 22 4 3 valid valid clk co(2:0) ci(2:0) 1 transfer of status information
3;%) data sheet 7-64 07.2000 (ohfwulfdo&kdudfwhulvwlfv 7deoh &dvfdgh,qwhuidfh7lplqj3dudphwhuv 1r 3dudphwhu /lplw9doxhv 8qlw plq w\s pd[ 1 clk frequency 0.01 25.92 mhz 2 co change from clk 22 ns 3 set up time to clk - 17 ns 4 hold time from clk - 2ns
3;%) data sheet 8-65 07.2000 3dfndjh2xwolqhv 3dfndjh2xwolqhv gpp05616 74)3 (144 pin thin plastic quad flatpack) )ljxuh 6ruwvri3dfnlqj package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
3;%) data sheet 9-66 07.2000 5hihuhqfhv 5hihuhqfhv 1. joint test action group jtag standard ieee std. 1149.1 $furq\pv abm pxb 4330 e $ tm % uffer 0 anager alp pxb 4350 e $ tm / ayer 3 rocessor aop pxb 4340 e $ tm 2 am 3 rocessor arc $ ddress 5 eduction & ircuit byte octet = 8 bits came & ontent $ ddressable 0 emory ( lement double word 32 bits f4 virtual path layer f5 virtual channel layer ht + eader 7 ranslation i/o , nput/ 2 utput ip , ntermediate 3 oint lci / ocal & onnection , dentifier lsb / east 6 ignificant % it octet byte = 8 bits oam 2 peration $ nd 0 aintenance pn 3 ort 1 umber ssram 6 ynchronous 6 tatic 5 andom $ ccess 0 emory tbd w o e e g efined tep 7 erminating ( nd 3 oint vcc 9 irtual & hannel & onnection vci 9 irtual & hannel , dentifier of standardized atm cell vp- 9 irtual 3 ath specific vpc 9 irtual 3 ath & onnection vpi 9 irtual 3 ath , dentifier of standardized atm cell word 16 bits

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